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S29AS008J70BHI040 Cypress Semiconductor 授權資源 & 價格優勢

  • S29AS008J70BHI040 - Cypress Semiconductor - 閃
  • S29AS008J70BHI040 - Cypress Semiconductor - 閃


圖片僅供參考
型號:
S29AS008J70BHI040
Worldway 型號:
S29AS008J70BHI040-321426
制造商:
Cypress Semiconductor
分類:
應用領域:
汽車行業 信息娛樂和集群 通訊設備 寬帶固定電話接入 產業 測試與測量
描述:

IC FLASH 8M PARALLEL 48FBGA

RoHS:
無鉛/符合RoHS
庫存狀態:
有現貨
庫存資源:
工廠剩餘庫存 / 特許經銷商
保證:
1年質量保證 » 了解更多
EDA/CAD模型:
S29AS008J70BHI040 PCB Footprint and Symbol
產品文檔:
S29AS008J70BHI040 產品文檔
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S29AS008J70BHI040(Cypress Semiconductor) 描述
Additional information about the S29AS008J70BHI040: The S29AS008J is a 8 Mbit, 1.8 Volt-only Flash memory organized as 1,048,576 bytes or 524,288 words with a x8/x16 bus and either top or bottom boot sector architecture. The device is offered in 48-pin TSOP and 48-ball FBGA packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed and erased in-system with the standard system 1.8 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not required for program or erase operations. The device can also be programmed in standard EPROM programmers. The device offers access time of 70 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The S29AS008J is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm— an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector group protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. Cypress Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
S29AS008J70BHI040(Cypress Semiconductor) 產品規格
Manufacturer: Cypress Semiconductor Corp
Product Category: Memory
Series: AS-J
Type: Boot Block
Packaging: Tray
Mounting-Style: SMD/SMT
Operating-Temperature-Range: - 40 C to + 85 C
Package-Case: 48-VFBGA
Operating-Temperature: -40°C ~ 85°C (TA)
Interface: Parallel
Voltage-Supply: 1.65 V ~ 1.95 V
Supplier-Device-Package: 48-FBGA (8.15x6.15)
Memory-Size: 8M (1M x 8 or 512K x 16)
Memory-Type: FLASH - NOR
Speed: 70ns
Architecture: Sector
Format-Memory: FLASH
Standard: Common Flash Interface (CFI)
Interface-Type: Parallel
Organization: 1 M x 8 512 k x 16
Supply-Current-Max: 30 mA
Data-Bus-Width: 8 bit 16 bit
Supply-Voltage-Max: 1.95 V
Supply-Voltage-Min: 1.65 V
Package-Case: BGA-48
Timing-Type: Asynchronous
其他授權供應商 (Worldway將從所有特許經營資源中提供最優惠的價格。)
Part # Manufacturer Description Stock Price
S29AS008J70BHI040 DISTI # S29AS008J70BHI040-ND
Cypress Semiconductor IC FLASH 8M PARALLEL 48FBGA RoHS: Compliant Min Qty: 676 Container: Tray Limited Supply - Call  
Part # Manufacturer Description Stock Price
S29AS008J70BHI040 DISTI # 727-S29AS008J70BHI04
Cypress Semiconductor NOR Flash Nor RoHS: Compliant 0  

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庫存狀態
有現貨
數量
30
交貨時間
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批號
1353+
數量限制
沒有限制
訂單最低
100 USD
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